Polycrystalline silicon films have been used in integrated circuits for many years, for example, the U.S. Pat. No. 3,558,374 by D. W. Boss et al. and assigned to the present assignee describes a method for controlling grain size of polycrystalline films so that PN junctions may be formed in the film.
The preferred polycrystalline silicon deposition process is thermal decomposition of silane either at reduced pressure and temperatures from 600.degree. C. to 700.degree. C. or at atmospheric pressure and temperatures of the order of 1000.degree. C. to 1200.degree. C. In most cases, the doping element has been introduced during the deposition process. Better control of the total amount of impurity is obtained if the conductivity imparting impurity is incorporated into the film after the deposition of the film by ion implantation. In that case, a post ion implantation annealing up to 1100.degree. C. is needed to assure uniform impurity distribution throughout the films.
The polycrystalline silicon films have been widely used in large scale integrated circuit devices, to provide gates for field effect transistor devices, device contact regions in bipolar transistors or as resistors. Process economies can be gained by using the available polycrystalline silicon films as resistors in large scale integrated circuits. The following patents and publications are examples of ion implanted polycrystalline silicon resistor methods and resulting products for a variety of uses. O. W. Hatcher, Jr. U.S. Pat. No. 3,432,792 describes a moat filled polycrystalline diffused resistor. M. W. Collver U.S. Pat. No. 4,063,210 describes a polycrystalline resistor having very small grain size and having dopants from the group consisting of nickel and cobalt dispersed in a super saturated solid solution in the film. B. G. Watkins et al. U.S. Pat. No. 3,576,478 describes a field effect transistor having a polycrystalline silicon resistor associated therewith. T. Masuhara et al. U.S. Pat. No. 4,199,778 describes the ion implantation of boron, phosphorus or arsenic into a polycrystalline silicon layer in the amount of about 1.times.10.sup.19 atoms/cm.sup.3 to form a polycrystalline silicon resistor. J. H. Raymond, Jr. U.S. Pat. Nos. 4,209,716 and 4,240,097 describes the method for manufacturing ion implanted lightly-doped polycrystalline silicon resistive layers which are useful as a load and a static RAM memory cell. R. W. Brower U.S. Pat. Nos. 4,210,465 and 4,212,684 describes method and resulting polycrystalline silicon structure wherein the polycrystalline silicon resistor is formed on a field silicon dioxide layer. K. L. Clark et al. U.S. Pat. No. 4,214,917 teaches the formation of a polycrystalline silicon resistor of relatively low resistivity by ion implantation with phosphorus with a dosage level in the general range of 10.sup.13 to 10.sup.14 ions/cm.sup.2. S. W. Miles et al. U.S. Pat. No. 4,256,515 describes the formation of high resistivity polycrystalline silicon resistors formed over the field silicon dioxide layer. The resistivity of the resistors is established by ion implantation of impurities such as boron. The J. R. Lloyd et al. Technical Disclosure Bulletin, Vol. 23, No. 7A, Dec. 1980, pp. 2811-2812 describe a polycrystalline silicon resistor fabrication which utilizes low energy ion implantation to dope a polycrystalline film to the desired resistivity. They describe a power level of about 10 to 500 KeV and a dosage of about 10.sup.12 to about 10.sup.17 ions/cm.sup.2 but for a film of about 500 nanometers in thickness. After the ion implantation the polycrystalline silicon is flash laser annealed to electrically activate the implanted impurities.